RTL Design & Verification Course ​

Learn the high in demand RTL Design and Verification course online delivered by best VLSI training institute in Bangalore, India. The course is derieved by industry professionals with 20+ years of experience.
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Design and Verification is an ASIC VLSI front-end course designed and delivered by trainers from the semiconductor industry as per the current technologies and requirements from the industry. This course emphasizes ASIC Design Flow, CMOS fundamentals, Advanced Digital Design, Verilog fundamentals, RTL Design using Verilog, and System Verilog.

Synthesis using industry-standard tools RTL Verification using Verilog and System Verilog covers Basics, Oops, assertion-based verification, Functional Coverage. Universal Verification methodologies. Also get all your VLSI design questions answered by our experts.

Every module is delivered with multiple projects to create a competitive spirit in the trainees.

6 Months

24/7 Lab Access

Hands on Learning

Industry Standard Tools

Multiple Industry Standard Projects

Interactive Virtual Classroom Training

Individual Course Option

Experienced Trainers

Detailed Curriculum

Who can attend?

  • Freshers who want to pursue a career in VLSI.
  • Embedded/FPGA Design engineers who want to switch to ASIC for career growth.
  • Corporates looking to get their engineers trained in RTL Design and Verification.
  • Working professionals from non-VLSI industry who want to switch for change or career growth.
  • Engineering graduates with BE, B.Tech, ME, M.Tech.
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Course Syllabus/Curriculum

This VLSI course comprises of four topics delivered over a period of 6 months.

1. UVM

The UVM syllabus covered by Silicon Yard is as under:

Examples using uvm_report_*

Examples using `uvm_*

Examples using copy clone, print, compare covering the fields automation macros like UVM_DEFAULT, UVM_ALL_ON

Covering the phases, creation of components, How new is quasistatic in the top-Down approach of Build_phase, rest phases are bottom-up multiple run_phases for raise and drop objections

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run_phase and sub_phases in parallel

uvm_blocking_put_port examples

Get port examples

Analysis port examples along with uvm_analysis_imp_dec

Creating a Driver, Sequencer along with sequences using responses completing the Macros used in sequences. Examples covering uvm_do uvm_do_with macros and using functions like uvm_create uvm_send and get_response

Examples covering uvm_do_on and uvm_do_on_with

Using config DB to set the virtual interface and environment configuration

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2. System Verilog for Verification

The System Verilog for Verification syllabus covered by Silicon Yard is as under:

Logic, reg, wire, bit, byte, int, short and long int, time literals, strings

Task and functions

Unary,binary and ternary operators

enum, typedef

join,join_none and join_any

Arrays (static and dynamic), packed and unpacked arrays, mailbox, queue, semaphores

Interfaces, clocking blocks, mod ports.

Functional and code coverage

Program block, delays (inter and intra) race conditions and event scheduler.

Transactor and its implementations.

Classes, OOP, nested classes, Statis and automatic tasks and functions, inheritance, encapsulations, abstractions, virtual methods and classes

Sarandon, Surandom_range, random seed, randomize, randomize with inline constraints using “inside” ,”dist” and implications operators

Using rand and rand and providing class bases constraints and methods to switch on /off the randomization and constraints, using inline constraints on objects, using for each loop in constraints

cover bins, cover points and cross-coverage

Interfaces, mod spots, Virtual Interfaces, Clocking Blocks.

Tasks and functions, Delays, race conditions, TB constrcuts, Self-checking test benches.

Directed vs random, functional verification process, stimulus generation, BFMS, Monitors and reference models, Coverage is driven verification, Verification planning, and management.

Verification plan, TB architecture, Coverage Models, Tracking simulation process, Building regression test suites. Test suit optimization

3. Verilog

4. Verification Project

Project specification analysis, Defining Verification Plan, Creating Test bench architecture, defining transactions, implementing the transactors:-Driver, Reciver and Scorebord. Implementing the Coverage model, Building the top-level Verification Environement, Defining Weighted random, Corner case, and dricted test cases. Building the regression suit. Generating the Coverage reports.

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Let Numbers Talk

Years of Experience
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Industry Partners
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Alumni Placed
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Learners On Online Platform
7000

What People Say

Some have called us the best VLSI training institute. We will let you see the reviews for yourself.
I think Silicon Yard is the best VLSI training institute in Bangalore because I learnt everything in one course. Even practical application through projects.
Sharan Sai
The UVM & Verilog videos helped me a lot in understandings concepts.
Pallavi
Silicon Yard is very good to learn and understand VLSI Design and Verilog language which gives the feel of classroom learning. If you want to enter the VLSI field, the Online VLSI DM course is very useful.
Laxmi
Amazing course explained by the Shoaib Sir. The lab projects and hands on learning helped me understand everything about the topic.
Aftab
Silicon Yard has got everything I needed. I really learnt a great deal from the trainings.
Dyanne G
Best VLSI training course as far as my experience. They cleared all my doubts as well and explained everything patiently.
Rajeev B

Choose your preferred registration plan

Weekday Course

  • 6 months
  • Monday to Friday
  • 7:30 PM to 9:00 PM
  • Complete RTL Design and Verification Syllabus
  • Best suited for engineering graduates
I want to Attend the Weekday Course

Weekend Course

  • 6 months
  • Saturdays and Sundays
  • 9:00 AM to 1:00 PM
  • Complete RTL Design and Verification Syllabus
  • Best suited for engineering graduates
Register for the weekend course